Integrated circuit performance is being continually improved by increasing device switching speed, increasing interconnection density and reducing cross-talk between adjacent conductors that are separated by inter-metal dielectric (IMD) layers. Switching speeds have been increased and cross-talk reduced by employing new dielectric thin film material as the IMD having low dielectric constant (“low-k material”), such as porous organo-silicate glass. Interconnections have been increased by increasing the number of interconnected conductive layers and reducing feature size (e.g., line widths, hole diameters). Connecting between different conductors entails high aspect ratio (deep and narrow) openings or “vias” through the low-k material. Such fine features (e.g., having feature sizes on the order of 45 nm) have required photoresist (for photolithography) adaptable to higher wavelengths. Such photoresist tends to be thinner and more prone to form imperfections such as pin holes or striations during the dielectric etch process. This problem is addressed by employing a fluorocarbon chemistry during the plasma etch formation of narrow vias though the low-k dielectric film. The fluorocarbon etch chemistry deposits a protective fluorocarbon polymer on the photoresist. The etch process typically must stop upon reaching a bottom dielectric layer overlying copper interconnection lines. This bottom dielectric layer typically serves as a barrier layer preventing diffusion of copper atoms from the conductor line, and is itself a low-k dielectric material, such as nitrogen-doped silicon carbide, and is typically very thin (on the order of hundreds of Angstroms). After the barrier layer has been exposed, the etch process is halted, having formed a deep narrow (high aspect ratio) opening or via. In preparation for the next process step, the photoresist is stripped from the wafer. This photoresist strip process can be done in an ammonia-based plasma with bias power applied to the wafer, and is performed in the same chamber in which the preceding etch process was performed, in order to avoid an unnecessary wafer transfer step and maximize productivity. The problem is that the photoresist strip process causes the thin barrier layer at the via bottom, consisting of the vulnerable low-k material, to disappear.
One way around this problem may be to transfer the wafer to a dedicated photoresist ashing chamber before performing the photoresist ashing step. Unfortunately, such an approach would reduce productivity because of the delays inherent in the transferring of the wafer between reactor chambers.
Therefore, there is a need for a combination via etch and photoresist strip process in which the thin barrier at the via bottom is preserved.